In a related technology, errors of transferred data are detected. For example, whether or not data includes an error may be detected by using a check code such as a parity bit, a cyclic redundancy check (CRC), or the like. Then, when the data may include an error, correction processing may be performed.
In addition, the following technology related to correction processing is proposed. For example, an error correction device may manipulate demodulated data whose reliability degree information bit indicating the likelihood of the demodulated data is at a given level, and thereby generate demodulated data patterns of all combinations that may be taken by the demodulated data pattern. The error correction device may perform error correction on the demodulated data patterns.
In addition, a technology is proposed which may generate data in a table format in advance, the data including remainders obtained by a generator polynomial for error correction and a plurality of correction patterns, perform error detection processing on corrected candidates corrected based on the plurality of correction patterns, and repeat the processing until it is determined that a remainder becomes zero and that correction is made. Related art is disclosed in Japanese Laid-open Patent Publication No. 08-330979 and Japanese Laid-open Patent Publication No. 2000-261326.